1. Field of the Invention
This invention relates to a method and an apparatus for estimating electric power consumption by integrated circuits which are comprised of basic cells and mega cells.
2. Description of the Related Art
As circuit components and systems thereof become exceedingly more complex, it is necessary to estimate power consumption by circuit components and integrated circuits with the highest possible accuracy. Several methods have heretofore been developed for estimating electric power consumed by integrated circuits and circuit components at the stage of circuit designing.
One conventional method is described in Japanese Laid-Open Patent Application 2-136775 which discloses a method that: (a) obtains numbers of operation events at terminals or pins of each basic cell from the results of logic simulations; and (b) estimates power consumption based on the number of events obtained and pre-established data of electric power consumption by each basic cell. Using this information the power consumed by an integrated circuit is estimated.
Another conventional method for power estimation of an integrated circuit is carried out by obtaining information on each basic cell: (a) changes in output voltage signals with time; (b) program instructions for the operation modes; and .COPYRGT. power consumption by the basic cells. Using this information the power consumed by an integrated circuit is estimated. Such a method is described in Japanese Laid-Open Patent Application 4-130661.
The above-mentioned conventional methods estimate power consumed by basic cells, but are insufficient to accurately estimate power consumption for integrated circuits including mega cells.
Therefore, it would be desirable to provide a method and an apparatus for estimating electric power consumed by integrated circuits and/or a circuit system which includes mega cells as well as basic cells.